diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index 722732e..56c6289 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -134,25 +134,52 @@
 	return (0);
 }
 
-void icache_enable (void)
+/* cache_bit must be either C1_IC or C1_DC */
+static void cache_enable(uint32_t cache_bit)
 {
-	ulong reg;
+	uint32_t reg;
 
-	reg = read_p15_c1 ();		/* get control reg. */
-	cp_delay ();
-	write_p15_c1 (reg | C1_IC);
+	reg = read_p15_c1();	/* get control reg. */
+	cp_delay();
+	write_p15_c1(reg | cache_bit);
 }
 
-void icache_disable (void)
+/* cache_bit must be either C1_IC or C1_DC */
+static void cache_disable(uint32_t cache_bit)
 {
-	ulong reg;
+	uint32_t reg;
 
-	reg = read_p15_c1 ();
-	cp_delay ();
-	write_p15_c1 (reg & ~C1_IC);
+	reg = read_p15_c1();
+	cp_delay();
+	write_p15_c1(reg & ~cache_bit);
 }
 
-int icache_status (void)
+void icache_enable(void)
 {
-	return (read_p15_c1 () & C1_IC) != 0;
+	cache_enable(C1_IC);
+}
+
+void icache_disable(void)
+{
+	cache_disable(C1_IC);
+}
+
+int icache_status(void)
+{
+	return (read_p15_c1() & C1_IC) != 0;
+}
+
+void dcache_enable(void)
+{
+	cache_enable(C1_DC);
+}
+
+void dcache_disable(void)
+{
+	cache_disable(C1_DC);
+}
+
+int dcache_status(void)
+{
+	return (read_p15_c1() & C1_DC) != 0;
 }
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 0e49e6c..7c860e5 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -137,6 +137,7 @@
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF	/* Needed to load Integrity kernel. */
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR